A COMPREHENSIVE REVIEW ON FAULT TOLERANCES, ROUTING TECHNICHES AND ENERGY EFFICIENCY IN NETWORK ON CHIP ARCHITECTURES

Abstract

All our modern processors are all belong to multicore processors. A new category of processors,where multiple processing units are housed on a single chip. According to Jordan Moore predicted that thenumber of transistors inside a chip is going to double every eighteen months. The advances in VLSI Innovations have brought out the Network-on-Chip (NoC) as an essential solution to handle the network communication issues in complex multi-core systems. Meanwhile, NoCs is a flexible and efficient solution for data communication within multi-core microprocessors as the complexity of semiconductor technology grows.

This survey paper makes a comprehensive analysis of the innovation, problem and application conduct that has been made by NoCs in multi-core systems. The paper starts with a background from where the focus is shifted to modern multi-core processors along with the significance of NoCs in improving the inter-core connectivity. For one, it makes a com-prehensive survey of NoC design parameters or strategies for topologies, routing algorithms, and protocols and unveils the extent of the influence of NoC designs on the performance and scalability effect of the NoC.

It also summarises the key limitations of NoC implementation that includes power management, reliability, and con-gestion control. Other important matters concerning the use and utilization of bandwidth and the issue of latency is also addressed as well provided us to squeeze in more number of transistors inside a chip. Package density of transistors hasincreased very high .More number of transistors inside chip permits us to include more number of functional units like processors, memory, control unit etc inside a chip. In the era of “Internet of Things and IOT and Artificial

Intelligence and threre is a requirement tocollect and process huge data ,and many of the applications are in real time ,which demands high computation power, a massive parallel computers.. To address these challenges, the paper offers solutions as follows, which are the new design strategies, energy efficient and fault tolerant schemes which en-deavour to improve on the overall performance of NoC as a design topology in large scale multiple core processing.

As is presented, potential uses of NoCs are identified in a number of novel application areas such as high-perfor-mance computing, IoT and artificial intelligence, demonstrating that NoC architectures maintain and enhance their rel-evance. Last, the paper discusses future work, and presents more details on why NoCs have to be adaptive, self-organizing structures, which will be sufficient for supporting multi-core systems of the next generation. NoC is a promising technol-ogy for multi core systems and this survey serves as a good starting point for researchers, engineers and technologists in this field.